/**
 * *****************************************************************
 * @file    gpio_ctype_map.h
 * @author  WuHao(hwu@andartechs.com.cn)
 * @version 1.0.0
 * @date    2020-11-24
 * @brief   gpio configuration registers address definition
 *
 *                 Copyright (c) 2020, Andar Technologies Inc.
 *                           www.andartechs.com 
 *
 * *****************************************************************
 */
#include "adt3102_type_define.h"
//#define gpio_int_state 0x00

//#define gpio_int_clear 0x01

//#define gpio_int_en 0x02

//#define gpio_int_edge_nlevel 0x03

//#define gpio_int_pol 0x04

//#define gpio_wake_pol 0x05

//#define gpio_wake_en 0x06

//#define gpio_out_set 0x08

//#define gpio_out_clear 0x09

//#define gpio_out_state 0x0a

//#define gpio_in 0x0b

//#define gpio_p00_config 0x0c
#define gpio_p00_config_p00_smt_bit (1<<11)
#define gpio_p00_config_p00_e_shift 9
#define gpio_p00_config_p00_e_mask ((1<<2)-1)
#define gpio_p00_config_p00_sr_bit (1<<8)
#define gpio_p00_config_p00_pu_bit (1<<7)
#define gpio_p00_config_p00_pd_bit (1<<6)
#define gpio_p00_config_p00_ie_bit (1<<5)
#define gpio_p00_config_p00_oen_bit (1<<4)
#define gpio_p00_config_p00_pid_shift 0
#define gpio_p00_config_p00_pid_mask ((1<<4)-1)

//#define gpio_p01_config 0x0d
#define gpio_p01_config_p01_smt_bit (1<<11)
#define gpio_p01_config_p01_e_shift 9
#define gpio_p01_config_p01_e_mask ((1<<2)-1)
#define gpio_p01_config_p01_sr_bit (1<<8)
#define gpio_p01_config_p01_pu_bit (1<<7)
#define gpio_p01_config_p01_pd_bit (1<<6)
#define gpio_p01_config_p01_ie_bit (1<<5)
#define gpio_p01_config_p01_oen_bit (1<<4)
#define gpio_p01_config_p01_pid_shift 0
#define gpio_p01_config_p01_pid_mask ((1<<4)-1)

//#define gpio_p02_config 0x0e
#define gpio_p02_config_p02_smt_bit (1<<11)
#define gpio_p02_config_p02_e_shift 9
#define gpio_p02_config_p02_e_mask ((1<<2)-1)
#define gpio_p02_config_p02_sr_bit (1<<8)
#define gpio_p02_config_p02_pu_bit (1<<7)
#define gpio_p02_config_p02_pd_bit (1<<6)
#define gpio_p02_config_p02_ie_bit (1<<5)
#define gpio_p02_config_p02_oen_bit (1<<4)
#define gpio_p02_config_p02_pid_shift 0
#define gpio_p02_config_p02_pid_mask ((1<<4)-1)

//#define gpio_p03_config 0x0f
#define gpio_p03_config_p03_smt_bit (1<<11)
#define gpio_p03_config_p03_e_shift 9
#define gpio_p03_config_p03_e_mask ((1<<2)-1)
#define gpio_p03_config_p03_sr_bit (1<<8)
#define gpio_p03_config_p03_pu_bit (1<<7)
#define gpio_p03_config_p03_pd_bit (1<<6)
#define gpio_p03_config_p03_ie_bit (1<<5)
#define gpio_p03_config_p03_oen_bit (1<<4)
#define gpio_p03_config_p03_pid_shift 0
#define gpio_p03_config_p03_pid_mask ((1<<4)-1)

//#define gpio_p04_config 0x10
#define gpio_p04_config_p04_smt_bit (1<<11)
#define gpio_p04_config_p04_e_shift 9
#define gpio_p04_config_p04_e_mask ((1<<2)-1)
#define gpio_p04_config_p04_sr_bit (1<<8)
#define gpio_p04_config_p04_pu_bit (1<<7)
#define gpio_p04_config_p04_pd_bit (1<<6)
#define gpio_p04_config_p04_ie_bit (1<<5)
#define gpio_p04_config_p04_oen_bit (1<<4)
#define gpio_p04_config_p04_pid_shift 0
#define gpio_p04_config_p04_pid_mask ((1<<4)-1)

//#define gpio_p05_config 0x11
#define gpio_p05_config_p05_smt_bit (1<<11)
#define gpio_p05_config_p05_e_shift 9
#define gpio_p05_config_p05_e_mask ((1<<2)-1)
#define gpio_p05_config_p05_sr_bit (1<<8)
#define gpio_p05_config_p05_pu_bit (1<<7)
#define gpio_p05_config_p05_pd_bit (1<<6)
#define gpio_p05_config_p05_ie_bit (1<<5)
#define gpio_p05_config_p05_oen_bit (1<<4)
#define gpio_p05_config_p05_pid_shift 0
#define gpio_p05_config_p05_pid_mask ((1<<4)-1)

//#define gpio_p06_config 0x12
#define gpio_p06_config_p06_smt_bit (1<<11)
#define gpio_p06_config_p06_e_shift 9
#define gpio_p06_config_p06_e_mask ((1<<2)-1)
#define gpio_p06_config_p06_sr_bit (1<<8)
#define gpio_p06_config_p06_pu_bit (1<<7)
#define gpio_p06_config_p06_pd_bit (1<<6)
#define gpio_p06_config_p06_ie_bit (1<<5)
#define gpio_p06_config_p06_oen_bit (1<<4)
#define gpio_p06_config_p06_pid_shift 0
#define gpio_p06_config_p06_pid_mask ((1<<4)-1)

//#define gpio_p07_config 0x13
#define gpio_p07_config_p07_smt_bit (1<<11)
#define gpio_p07_config_p07_e_shift 9
#define gpio_p07_config_p07_e_mask ((1<<2)-1)
#define gpio_p07_config_p07_sr_bit (1<<8)
#define gpio_p07_config_p07_pu_bit (1<<7)
#define gpio_p07_config_p07_pd_bit (1<<6)
#define gpio_p07_config_p07_ie_bit (1<<5)
#define gpio_p07_config_p07_oen_bit (1<<4)
#define gpio_p07_config_p07_pid_shift 0
#define gpio_p07_config_p07_pid_mask ((1<<4)-1)

//#define gpio_p08_config 0x14
#define gpio_p08_config_p08_smt_bit (1<<11)
#define gpio_p08_config_p08_e_shift 9
#define gpio_p08_config_p08_e_mask ((1<<2)-1)
#define gpio_p08_config_p08_sr_bit (1<<8)
#define gpio_p08_config_p08_pu_bit (1<<7)
#define gpio_p08_config_p08_pd_bit (1<<6)
#define gpio_p08_config_p08_ie_bit (1<<5)
#define gpio_p08_config_p08_oen_bit (1<<4)
#define gpio_p08_config_p08_pid_shift 0
#define gpio_p08_config_p08_pid_mask ((1<<4)-1)

//#define gpio_p09_config 0x15
#define gpio_p09_config_p09_smt_bit (1<<11)
#define gpio_p09_config_p09_e_shift 9
#define gpio_p09_config_p09_e_mask ((1<<2)-1)
#define gpio_p09_config_p09_sr_bit (1<<8)
#define gpio_p09_config_p09_pu_bit (1<<7)
#define gpio_p09_config_p09_pd_bit (1<<6)
#define gpio_p09_config_p09_ie_bit (1<<5)
#define gpio_p09_config_p09_oen_bit (1<<4)
#define gpio_p09_config_p09_pid_shift 0
#define gpio_p09_config_p09_pid_mask ((1<<4)-1)

//#define gpio_p10_config 0x16
#define gpio_p10_config_p10_smt_bit (1<<11)
#define gpio_p10_config_p10_e_shift 9
#define gpio_p10_config_p10_e_mask ((1<<2)-1)
#define gpio_p10_config_p10_sr_bit (1<<8)
#define gpio_p10_config_p10_pu_bit (1<<7)
#define gpio_p10_config_p10_pd_bit (1<<6)
#define gpio_p10_config_p10_ie_bit (1<<5)
#define gpio_p10_config_p10_oen_bit (1<<4)
#define gpio_p10_config_p10_pid_shift 0
#define gpio_p10_config_p10_pid_mask ((1<<4)-1)

//#define gpio_p11_config 0x17
#define gpio_p11_config_p11_smt_bit (1<<11)
#define gpio_p11_config_p11_e_shift 9
#define gpio_p11_config_p11_e_mask ((1<<2)-1)
#define gpio_p11_config_p11_sr_bit (1<<8)
#define gpio_p11_config_p11_pu_bit (1<<7)
#define gpio_p11_config_p11_pd_bit (1<<6)
#define gpio_p11_config_p11_ie_bit (1<<5)
#define gpio_p11_config_p11_oen_bit (1<<4)
#define gpio_p11_config_p11_pid_shift 0
#define gpio_p11_config_p11_pid_mask ((1<<4)-1)

//#define gpio_p12_config 0x18
#define gpio_p12_config_p12_smt_bit (1<<11)
#define gpio_p12_config_p12_e_shift 9
#define gpio_p12_config_p12_e_mask ((1<<2)-1)
#define gpio_p12_config_p12_sr_bit (1<<8)
#define gpio_p12_config_p12_pu_bit (1<<7)
#define gpio_p12_config_p12_pd_bit (1<<6)
#define gpio_p12_config_p12_ie_bit (1<<5)
#define gpio_p12_config_p12_oen_bit (1<<4)
#define gpio_p12_config_p12_pid_shift 0
#define gpio_p12_config_p12_pid_mask ((1<<4)-1)

//#define gpio_p13_config 0x19
#define gpio_p13_config_p13_smt_bit (1<<11)
#define gpio_p13_config_p13_e_shift 9
#define gpio_p13_config_p13_e_mask ((1<<2)-1)
#define gpio_p13_config_p13_sr_bit (1<<8)
#define gpio_p13_config_p13_pu_bit (1<<7)
#define gpio_p13_config_p13_pd_bit (1<<6)
#define gpio_p13_config_p13_ie_bit (1<<5)
#define gpio_p13_config_p13_oen_bit (1<<4)
#define gpio_p13_config_p13_pid_shift 0
#define gpio_p13_config_p13_pid_mask ((1<<4)-1)

//#define gpio_p14_config 0x1a
#define gpio_p14_config_p14_smt_bit (1<<11)
#define gpio_p14_config_p14_e_shift 9
#define gpio_p14_config_p14_e_mask ((1<<2)-1)
#define gpio_p14_config_p14_sr_bit (1<<8)
#define gpio_p14_config_p14_pu_bit (1<<7)
#define gpio_p14_config_p14_pd_bit (1<<6)
#define gpio_p14_config_p14_ie_bit (1<<5)
#define gpio_p14_config_p14_oen_bit (1<<4)
#define gpio_p14_config_p14_pid_shift 0
#define gpio_p14_config_p14_pid_mask ((1<<4)-1)

//#define gpio_p15_config 0x1b
#define gpio_p15_config_p15_smt_bit (1<<11)
#define gpio_p15_config_p15_e_shift 9
#define gpio_p15_config_p15_e_mask ((1<<2)-1)
#define gpio_p15_config_p15_sr_bit (1<<8)
#define gpio_p15_config_p15_pu_bit (1<<7)
#define gpio_p15_config_p15_pd_bit (1<<6)
#define gpio_p15_config_p15_ie_bit (1<<5)
#define gpio_p15_config_p15_oen_bit (1<<4)
#define gpio_p15_config_p15_pid_shift 0
#define gpio_p15_config_p15_pid_mask ((1<<4)-1)

//#define gpio_p16_config 0x1c
#define gpio_p16_config_p16_smt_bit (1<<11)
#define gpio_p16_config_p16_e_shift 9
#define gpio_p16_config_p16_e_mask ((1<<2)-1)
#define gpio_p16_config_p16_sr_bit (1<<8)
#define gpio_p16_config_p16_pu_bit (1<<7)
#define gpio_p16_config_p16_pd_bit (1<<6)
#define gpio_p16_config_p16_ie_bit (1<<5)
#define gpio_p16_config_p16_oen_bit (1<<4)
#define gpio_p16_config_p16_pid_shift 0
#define gpio_p16_config_p16_pid_mask ((1<<4)-1)

//#define gpio_p17_config 0x1d
#define gpio_p17_config_p17_smt_bit (1<<11)
#define gpio_p17_config_p17_e_shift 9
#define gpio_p17_config_p17_e_mask ((1<<2)-1)
#define gpio_p17_config_p17_sr_bit (1<<8)
#define gpio_p17_config_p17_pu_bit (1<<7)
#define gpio_p17_config_p17_pd_bit (1<<6)
#define gpio_p17_config_p17_ie_bit (1<<5)
#define gpio_p17_config_p17_oen_bit (1<<4)
#define gpio_p17_config_p17_pid_shift 0
#define gpio_p17_config_p17_pid_mask ((1<<4)-1)

//#define gpio_p18_config 0x1e
#define gpio_p18_config_p18_smt_bit (1<<11)
#define gpio_p18_config_p18_e_shift 9
#define gpio_p18_config_p18_e_mask ((1<<2)-1)
#define gpio_p18_config_p18_sr_bit (1<<8)
#define gpio_p18_config_p18_pu_bit (1<<7)
#define gpio_p18_config_p18_pd_bit (1<<6)
#define gpio_p18_config_p18_ie_bit (1<<5)
#define gpio_p18_config_p18_oen_bit (1<<4)
#define gpio_p18_config_p18_pid_shift 0
#define gpio_p18_config_p18_pid_mask ((1<<4)-1)

//#define gpio_p19_config 0x1f
#define gpio_p19_config_p19_smt_bit (1<<11)
#define gpio_p19_config_p19_e_shift 9
#define gpio_p19_config_p19_e_mask ((1<<2)-1)
#define gpio_p19_config_p19_sr_bit (1<<8)
#define gpio_p19_config_p19_pu_bit (1<<7)
#define gpio_p19_config_p19_pd_bit (1<<6)
#define gpio_p19_config_p19_ie_bit (1<<5)
#define gpio_p19_config_p19_oen_bit (1<<4)
#define gpio_p19_config_p19_pid_shift 0
#define gpio_p19_config_p19_pid_mask ((1<<4)-1)

//#define gpio_p20_config 0x20
#define gpio_p20_config_p20_smt_bit (1<<11)
#define gpio_p20_config_p20_e_shift 9
#define gpio_p20_config_p20_e_mask ((1<<2)-1)
#define gpio_p20_config_p20_sr_bit (1<<8)
#define gpio_p20_config_p20_pu_bit (1<<7)
#define gpio_p20_config_p20_pd_bit (1<<6)
#define gpio_p20_config_p20_ie_bit (1<<5)
#define gpio_p20_config_p20_oen_bit (1<<4)
#define gpio_p20_config_p20_pid_shift 0
#define gpio_p20_config_p20_pid_mask ((1<<4)-1)

//#define gpio_p21_config 0x21
#define gpio_p21_config_p21_smt_bit (1<<11)
#define gpio_p21_config_p21_e_shift 9
#define gpio_p21_config_p21_e_mask ((1<<2)-1)
#define gpio_p21_config_p21_sr_bit (1<<8)
#define gpio_p21_config_p21_pu_bit (1<<7)
#define gpio_p21_config_p21_pd_bit (1<<6)
#define gpio_p21_config_p21_ie_bit (1<<5)
#define gpio_p21_config_p21_oen_bit (1<<4)
#define gpio_p21_config_p21_pid_shift 0
#define gpio_p21_config_p21_pid_mask ((1<<4)-1)

//#define gpio_p22_config 0x22
#define gpio_p22_config_p22_smt_bit (1<<11)
#define gpio_p22_config_p22_e_shift 9
#define gpio_p22_config_p22_e_mask ((1<<2)-1)
#define gpio_p22_config_p22_sr_bit (1<<8)
#define gpio_p22_config_p22_pu_bit (1<<7)
#define gpio_p22_config_p22_pd_bit (1<<6)
#define gpio_p22_config_p22_ie_bit (1<<5)
#define gpio_p22_config_p22_oen_bit (1<<4)
#define gpio_p22_config_p22_pid_shift 0
#define gpio_p22_config_p22_pid_mask ((1<<4)-1)

//#define gpio_p23_config 0x23
#define gpio_p23_config_p23_smt_bit (1<<11)
#define gpio_p23_config_p23_e_shift 9
#define gpio_p23_config_p23_e_mask ((1<<2)-1)
#define gpio_p23_config_p23_sr_bit (1<<8)
#define gpio_p23_config_p23_pu_bit (1<<7)
#define gpio_p23_config_p23_pd_bit (1<<6)
#define gpio_p23_config_p23_ie_bit (1<<5)
#define gpio_p23_config_p23_oen_bit (1<<4)
#define gpio_p23_config_p23_pid_shift 0
#define gpio_p23_config_p23_pid_mask ((1<<4)-1)

//#define gpio_p24_config 0x24
#define gpio_p24_config_p24_smt_bit (1<<11)
#define gpio_p24_config_p24_e_shift 9
#define gpio_p24_config_p24_e_mask ((1<<2)-1)
#define gpio_p24_config_p24_sr_bit (1<<8)
#define gpio_p24_config_p24_pu_bit (1<<7)
#define gpio_p24_config_p24_pd_bit (1<<6)
#define gpio_p24_config_p24_ie_bit (1<<5)
#define gpio_p24_config_p24_oen_bit (1<<4)
#define gpio_p24_config_p24_pid_shift 0
#define gpio_p24_config_p24_pid_mask ((1<<4)-1)

//#define gpio_p25_config 0x25
#define gpio_p25_config_p25_smt_bit (1<<11)
#define gpio_p25_config_p25_e_shift 9
#define gpio_p25_config_p25_e_mask ((1<<2)-1)
#define gpio_p25_config_p25_sr_bit (1<<8)
#define gpio_p25_config_p25_pu_bit (1<<7)
#define gpio_p25_config_p25_pd_bit (1<<6)
#define gpio_p25_config_p25_ie_bit (1<<5)
#define gpio_p25_config_p25_oen_bit (1<<4)
#define gpio_p25_config_p25_pid_shift 0
#define gpio_p25_config_p25_pid_mask ((1<<4)-1)

//#define gpio_p26_config 0x26
#define gpio_p26_config_p26_smt_bit (1<<11)
#define gpio_p26_config_p26_e_shift 9
#define gpio_p26_config_p26_e_mask ((1<<2)-1)
#define gpio_p26_config_p26_sr_bit (1<<8)
#define gpio_p26_config_p26_pu_bit (1<<7)
#define gpio_p26_config_p26_pd_bit (1<<6)
#define gpio_p26_config_p26_ie_bit (1<<5)
#define gpio_p26_config_p26_oen_bit (1<<4)
#define gpio_p26_config_p26_pid_shift 0
#define gpio_p26_config_p26_pid_mask ((1<<4)-1)

//#define gpio_p27_config 0x27
#define gpio_p27_config_p27_smt_bit (1<<11)
#define gpio_p27_config_p27_e_shift 9
#define gpio_p27_config_p27_e_mask ((1<<2)-1)
#define gpio_p27_config_p27_sr_bit (1<<8)
#define gpio_p27_config_p27_pu_bit (1<<7)
#define gpio_p27_config_p27_pd_bit (1<<6)
#define gpio_p27_config_p27_ie_bit (1<<5)
#define gpio_p27_config_p27_oen_bit (1<<4)
#define gpio_p27_config_p27_pid_shift 0
#define gpio_p27_config_p27_pid_mask ((1<<4)-1)

//#define gpio_p28_config 0x28
#define gpio_p28_config_p28_smt_bit (1<<11)
#define gpio_p28_config_p28_e_shift 9
#define gpio_p28_config_p28_e_mask ((1<<2)-1)
#define gpio_p28_config_p28_sr_bit (1<<8)
#define gpio_p28_config_p28_pu_bit (1<<7)
#define gpio_p28_config_p28_pd_bit (1<<6)
#define gpio_p28_config_p28_ie_bit (1<<5)
#define gpio_p28_config_p28_oen_bit (1<<4)
#define gpio_p28_config_p28_pid_shift 0
#define gpio_p28_config_p28_pid_mask ((1<<4)-1)

//#define gpio_p29_config 0x29
#define gpio_p29_config_p29_smt_bit (1<<11)
#define gpio_p29_config_p29_e_shift 9
#define gpio_p29_config_p29_e_mask ((1<<2)-1)
#define gpio_p29_config_p29_sr_bit (1<<8)
#define gpio_p29_config_p29_pu_bit (1<<7)
#define gpio_p29_config_p29_pd_bit (1<<6)
#define gpio_p29_config_p29_ie_bit (1<<5)
#define gpio_p29_config_p29_oen_bit (1<<4)
#define gpio_p29_config_p29_pid_shift 0
#define gpio_p29_config_p29_pid_mask ((1<<4)-1)

//#define gpio_p30_config 0x2a
#define gpio_p30_config_p30_smt_bit (1<<11)
#define gpio_p30_config_p30_e_shift 9
#define gpio_p30_config_p30_e_mask ((1<<2)-1)
#define gpio_p30_config_p30_sr_bit (1<<8)
#define gpio_p30_config_p30_pu_bit (1<<7)
#define gpio_p30_config_p30_pd_bit (1<<6)
#define gpio_p30_config_p30_ie_bit (1<<5)
#define gpio_p30_config_p30_oen_bit (1<<4)
#define gpio_p30_config_p30_pid_shift 0
#define gpio_p30_config_p30_pid_mask ((1<<4)-1)

//#define gpio_sw_dis 0x2b

//#define gpio_bbadc_test 0x2c
#define gpio_bbadc_test_test_cnt_fix_shift 4
#define gpio_bbadc_test_test_cnt_fix_mask ((1<<3)-1)
#define gpio_bbadc_test_test_cnt_sel_shift 2
#define gpio_bbadc_test_test_cnt_sel_mask ((1<<2)-1)
#define gpio_bbadc_test_test_adc_iq_sel_bit (1<<1)
#define gpio_bbadc_test_test_adc_ddr_out_sel_bit (1<<0)

// GPIO 
typedef struct
{
  __IO uint32 gpio_int_state ;
  __IO uint32 gpio_int_clear ;
  __IO uint32 gpio_int_en ;
  __IO uint32 gpio_int_edge_nlevel ;
  __IO uint32 gpio_int_pol ;
  __IO uint32 gpio_wake_pol ;
  __IO uint32 gpio_wake_en ;
       uint32 reserve0[1] ;
  __IO uint32 gpio_out_set ;
  __IO uint32 gpio_out_clear ;
  __IO uint32 gpio_out_state ;
  __IO uint32 gpio_in ;
  __IO uint32 gpio_p00_config ;
  __IO uint32 gpio_p01_config ;
  __IO uint32 gpio_p02_config ;
  __IO uint32 gpio_p03_config ;
  __IO uint32 gpio_p04_config ;
  __IO uint32 gpio_p05_config ;
  __IO uint32 gpio_p06_config ;
  __IO uint32 gpio_p07_config ;
  __IO uint32 gpio_p08_config ;
  __IO uint32 gpio_p09_config ;
  __IO uint32 gpio_p10_config ;
  __IO uint32 gpio_p11_config ;
  __IO uint32 gpio_p12_config ;
  __IO uint32 gpio_p13_config ;
  __IO uint32 gpio_p14_config ;
  __IO uint32 gpio_p15_config ;
  __IO uint32 gpio_p16_config ;
  __IO uint32 gpio_p17_config ;
  __IO uint32 gpio_p18_config ;
  __IO uint32 gpio_p19_config ;
  __IO uint32 gpio_p20_config ;
  __IO uint32 gpio_p21_config ;
  __IO uint32 gpio_p22_config ;
  __IO uint32 gpio_p23_config ;
  __IO uint32 gpio_p24_config ;
  __IO uint32 gpio_p25_config ;
  __IO uint32 gpio_p26_config ;
  __IO uint32 gpio_p27_config ;
  __IO uint32 gpio_p28_config ;
  __IO uint32 gpio_p29_config ;
  __IO uint32 gpio_p30_config ;
  __IO uint32 gpio_sw_dis ;
  __IO uint32 gpio_bbadc_test ;
}GPIO_TypeDef;
